Input/output (I/O) circuits are commonly used for transferring data to and from an integrated circuit or other type of electronic device. For example, a programmable logic device such as a field programmable gate array (FPGA) or a complex programmable logic device (CPLD) will have a plurality of I/O circuits, where each I/O circuit corresponds to a pin of the FPGA. These I/O circuits (also referred to as input/output buffers, receiver/transmitter circuits, or receiver/driver circuits) typically support a variety of I/O interface standards (e.g., low voltage differential signaling (LVDS), high-speed transceiver logic (HSTL), or LVCMOS). These I/O interface standards generally address chip-to-chip interfaces, board-to-board interfaces, and box-to-box interfaces for a wide range of existing and emerging applications, such as data packet processing, data bus bridges, and high-speed memory interfacing.
Depending upon the I/O standard used in a given I/O buffer, the required supply voltage (VCC level) will vary. For example, typical supply voltages are 2.5 volt, 1.8 volt, 1.5 volt, and 1.2 volt. To permit FPGAs to operate using signals from multiple I/O standards requiring differing supply voltages, the I/O buffers are typically organized into banks. Each bank includes a plurality of I/O buffers and their corresponding pins and is configured to operate on a supply voltage supplied by a selected power supply. In this fashion, different banks of I/O buffers may operate using different supply voltages.
In the bank-based approach to organizing I/O buffers for FPGAs, the input buffer within each I/O buffer may be programmable for reference receiver operation. In reference receiver operation, the input buffer compares a received voltage to a reference voltage to make a bit decision. A voltage rail carrying the reference voltage spa the I/O buffers in each bank so that each I/O buffer may access the reference voltage during reference receiver operation. Certain I/O buffers within each bank are specialized to receive the reference voltage and couple it to the corresponding voltage rail. FIG. 1 illustrates a conventional input buffer 80 configured for reference receiver operation. A push-pull buffer 85 either pushes a current into an input lead 82 or pulls a current from input lead 82 depending upon the logical state of the data bit 90 being driven by push-pull buffer 85. Input buffer 80 couples to input lead 82, which also couples to a terminating resistor 95 receiving a terminating voltage VTT. The terminating voltage VTT is typically one-half the value of the supply voltage VDD powering the push-pull buffer 85. Input buffer 80 forms a comparator that compares the voltage on input lead 82 to the reference voltage and drives a received signal 84 either high or low. When push-pull buffer 85 pulls a current from input lead 82, the voltage on input lead 82 will tend to be pulled below the reference voltage, causing input buffer 80 to drive the received signal 84 into the corresponding logical state. Similarly, when push-pull buffer 85 drives a current into input lead 82, the voltage on input lead 82 will tend to be driven above the reference voltage, causing input buffer 80 to drive received signal 84 into the complement logical state. Input buffer 80 would be organized within a bank of input buffers all sharing the same supply voltage VDD. A specialized input buffer within the bank supplies the reference voltage.
Although the bank-based approach to organizing I/O buffers allows an FPGA to operate with multiple I/O standards requiring differing supply voltages, the approach suffers a number of drawbacks. For example, the routing of external signals to each bank is hindered because the voltage reference can be received only at the I/O buffers that are specialized for this function. In addition, no provision is made for utilizing multiple voltage references within a single bank.
Accordingly, there is a need in the art for improved bank-based approaches to I/O buffer organization for programmable logic devices that provide users with greater routing flexibility and improved I/O buffer utilization efficiency.